1. Field of the Invention
Embodiments of the present invention relate generally to cameras and methods and, in specific embodiments, to cameras and methods with an image sensor, data processing, and memory.
2. Related Art
Cameras have found wide application as consumer and industrial devices, and the development of image sensors has enabled an explosion in a number of digital cameras used for work and entertainment. FIG. 1 illustrates the architecture of a related art high speed camera 60 with an image sensor 62, a high-end Field-Programmable Gate Array (FPGA) 64 configured to perform on-the-fly image pre-processing, a memory 66, and output interfaces 68. The image sensor 62 samples light intensity of a scene being imaged and outputs digital pixel values from output data ports 63.
High speed digital Complementary Metal-Oxide-Semiconductor (CMOS) image sensors typically have multiple output data ports. An example of a high speed CMOS image sensor is the AM41V4™ image sensor by Alexima, which has 4 ports in each sensor corner that are 10 bits each for a total of 16 ports at 10 bits each or 160 digital outputs. The AM41V4™ image sensor is described in the document entitled “AM41V4, AM41V4ZC 4MPIX 500FPS CMOS Image Sensor,” by Alexima, dated Jun. 5, 2012. Some image sensors may have digital output ports on only one side of the image sensor, while other image sensors may have digital output ports split between two sides of the image sensors, and yet other image sensors may have digital output ports in each corner (as in the image sensor 62 in FIG. 1). Some image sensors may have as many groups of ports as there are memory blocks in the image sensors.
Each of the ports 63 of the image sensor 62 is connected to a corresponding pin of the high-end FPGA 64. In a typical implementation of the high speed camera 60, all data from all of the parallel sensor ports 63 are imported into the one large, wide interface, high processing power, high cost, high-end FPGA 64, which may be, for example, a Virtex-6™ FPGA by Xilinx Inc. or a Stratix IV™ FPGA by Altera Corporation. The high-end FPGA is also connected to the memory 66 by a connection 65 and to the output interfaces 68 by a connection 67. During an image capture operation of the camera 60, high speed image data from the image sensor 62 is written by the high-end FPGA 64 into the memory 66 up to its full capacity. Then, after the image has been captured, a retrieving of the data from the memory 66 by the high-end FPGA 64 may be done at slow speed to be provided to the output interfaces 68, as the commercially available output interfaces 68 from the camera, such as Gigabit Ethernet, Universal Serial Bus (USB)-2, or USB-3, are relatively slow interfaces.